1. Field of the Invention
The present invention relates to the deposition of tungsten-containing material on substrates used in semiconductor manufacture. More particularly, the invention relates to controlling the deposition of tungsten at the edges of circumferential semiconductor substrates.
2. Description of the Prior Art
Chemical vapor deposition, commonly referred to as "CVD," is one of a number of processes used to deposit thin layers of materials on a semiconductor wafer. To process wafers with the CVD process, a vacuum chamber is provided with a susceptor configured to receive a wafer thereon. In a typical prior art CVD chamber, the wafer is placed into and removed from the chamber by a robot blade and is supported by the susceptor during processing. In these typical systems, the susceptor and the wafer are heated to a temperature of between 200-650.degree. C. prior to processing. Once the wafer is heated to an appropriate temperature, a processing fluid, typically a gas, is charged to the vacuum chamber through a gas manifold often situated above the wafer. The processing gas reacts with the heated wafer surface to deposit a thin material layer thereon. As the gas thermally reacts to form the material layer, volatile byproduct gases are formed, and these gases are pumped out of the vacuum chamber through a chamber exhaust system.
A primary goal of wafer processing is to obtain as many useful die as possible from each wafer. Many factors influence the processing of wafers in the CVD chamber and affect the ultimate yield of die from each wafer processed therein. These factors include processing variables which affect the uniformity and thickness of the material layer deposited on the wafer, and particulate contaminants that can attach to a wafer and contaminate one or more die therein. Both of these factors must be controlled in CVD and other processes to maximize the die yield from each wafer.
One of the causes of particulate contaminants both in the chamber and on a finished wafer is improper deposition at the edge of the substrates. Because edge deposition conditions are difficult to control, due in part to the fact that substrates edges are typically chamferred and deposition gas flow is non-uniform around these edges, non-uniform deposition can occur around a substrate's edge. This may lead to deposited layers not adhering properly to each other and/or not adhering properly to the substrate.
This problem is illustrated in FIG. 1 which is a schematic partial cross-section of a semiconductor substrate. The substrate 1 is shown with three consecutive layers, 2,3 and 4, deposited thereon. In the deposition of tungsten on the substrate (using WF.sub.6 gas) the first layer 2 could typically be titanium, the second layer 3 would be titanium nitride, and the third (upper) layer 4 would be tungsten. Such a three-layer process for the deposition of tungsten is common as tungsten does not readily adhere to the silicon (or oxidized silicon) surface of the substrate. Accordingly, a very thin "primer" layer 2 of titanium is deposited, followed by a second layer 3 of titanium nitride. Tungsten readily adheres to titanium nitride (TiN). As can be seen from FIG. 1, however, the tungsten layer 4 has "wrapped" around onto the beveled outer edge 5 of the substrate to contact directly with the silicon substrate. The problem with this wrap-around adhesion is that tungsten does not adhere to the silicon substrate surface and could readily chip and flake during the handling of the substrate, resulting in particulate contaminants.
Multiple-layered semiconductor configurations are presently very prominent in the manufacture of large-scale integrated circuits. In these multilayered semiconductor devices, the formation of the electrical wiring connecting the layers is critical to the complex semiconductor devices. Additionally, in the formation of multiple-layered semiconductor substrates, planarization technology has also become critical to making optimum flat surfaces to accommodate a multilayerd electrode wiring structure.
In the application of tungsten material to form the electrode wiring resulting in low resistance interconnects in VLSI circuits, CVD methods are known. For example, as demonstrated in FIG. 10, a tungsten nucleation film of oxide 204, which serves as the nucleus for forming a film of tungsten material, is formed on a semiconductor substrate generally comprised of multiple layers having metal wire interconnects 200 distributed therein. Subsequently, a blanket film of tungsten material 206 is applied forming further metal wiring interconnects, and planarization or flattening is accomplished by means of an etchback process which etch-flattens the entire surface of said tungsten film. Note here that the bevelled edge deposition of tungsten adheres to the oxide layer 204 in the same fragile manner as demonstrated in FIG. 1.
In recent planarization technology for semiconductor wafers, a contact-type polishing method called CMP (chemical mechanical polishing) has become prominent. The CMP method achieves flattening or planarization by mechanically polishing the irregular surface generally accompanying a fabricated multilayered semiconductor wafer structure. In this CMP process, a chemical polishing agent and pad are employed to homogeneously polish the wafer. Because of the contact polishing of the wafer in the CMP process, the polished wafer surface becomes more uniformly flatter compared to the etchback method, so a precise multilayered electrode wiring structure can be achieved. However, as pointed out above with reference to FIG. 1, the outer peripheral edge of a tungsten-coated semiconductor wafer is generally chamferred, thereby causing the tungsten layer to deposit directly on the silicon substrate with which tungsten does not readily adhere. This unstable edge-deposited tungsten is readily removed during chemical-mechanical polishing thereby contaminating both the polishing process and the wafer itself with unwanted particles of tungsten strewn over the polishing pad and wafer surface.